The present invention relates to a fabrication method of a semiconductor device, and more particularly, to a method for fabricating a semiconductor method, which can accurately overlap a storage node contact plug with a storage node.
In dynamic random access memory (DRAM), a storage node (SN) must be designed to have a maximum area in order to secure a capacitance of a capacitor. The storage node (SN) must be arranged in a zigzag form in order to obtain a maximum area within a limited cell area. The zigzag arrangement, however, causes a misalignment of the storage node (SN) and a storage node contact (SNC) disposed thereunder. To solve the misalignment, another storage node contact (SNC2) is formed between the storage node (SN) and the storage node contact (SNC) to connect them to each other.
FIG. 1 illustrates a typical method for forming a storage node. A plurality of gate patterns 12 are formed over a substrate 11 where a device isolation structure is formed. Gate spacers 13 are formed on sidewalls of the gate patterns 12.
A landing plug contact 14 is formed between the gate patterns 12. A first insulating layer 15 and a second insulating layer 16 are sequentially formed over the resulting structure. The second insulating layer 16 and the first insulating layer 15 are etched to form a storage node contact hole (not indicated by a reference numeral). Thereafter, the storage node contact hole is filled to form a storage node contact (SNC) plug 17.
A third insulating layer 18 is formed over the resulting structure with the SNC plug 17. Another storage node contact (SNC2) plug 19 is formed in the third insulating layer 18. The SNC2 plug 19 passes through the third insulating layer 18 and is connected to the SNC plug 17. In forming the SNC2 plug 19, an SNC2 mask is required. The third insulating layer 18 is etched using the SNC2 mask as an etch barrier to thereby form an SNC2 contact hole. Then, the SNC2 contact hole is filled to form the SNC2 plug 19. The processes of forming the SNC2 mask, the SNC2 contact hole, and the SNC2 plug will be referred to as an SNC2 process. A fourth insulating layer 20 is formed over the SNC2 plug 19 and is then etched to form a hole. The hole is filled to form a storage node 21. In the typical method shown in FIG. 1, the SNC2 plug 19 is formed between the SNC plug 17 and the storage node 21 to connect them to each other in the middle of the misaligned structure.
FIG. 2 illustrates a layout diagram of a typical connection relationship of SNC plugs, storage nodes, and SNC2 plugs. According to the typical method of FIG. 1, however, the SNC2 process requires additional processes, including the SNC2 mask process (using ArF), which is a threshold layer mask step. Consequently, the SNC2 process leads to increase in a turn around time (TAT) and a manufacturing cost. Moreover, an unnecessary interface is formed between the SNC plug 17 and the SNC2 plug 19, increasing a contact resistance.